Radio frequency complementary metal oxide (RFCMOS) silicon-on-insulator (SOI) RF power switches are devices that are essential for practically every mobile handset currently on the market. Existing RFCMOS SOI technologies used to manufacture these devices provide excellent performance in increasingly complex multi-throw RF switches, tunable RF capacitance arrays, and antenna RF tuners. Conventional RFCMOS SOI technologies are built on high resistivity CMOS wafer handles that have resistivities ranging from 1000 Ohm-cm to 5000 Ohm-cm. A power switch employing RFCMOS SOI technology uses a high resistivity wafer handle so that a plurality of relatively low voltage field effect transistors (FETs) can be stacked while maintaining a desired isolation between the low voltage FETs.
In an RF switch application for third generation (3G) and fourth generation (4G) wireless applications, a high degree of RF device linearity and a relatively very low level of RF intermodulation under RF power conditions are crucial. Therefore, inherent nonlinearities in RF devices such as CMOS n-type field effect transistor (NFET) devices must be mitigated. Another source of nonlinearities is attributed to a high resistivity silicon wafer handle region interfaced with a buried oxide (BOX) dielectric region. One proposed solution for mitigating these nonlinearities includes a trap rich silicon/oxide interface that degrades carrier lifetimes in the silicon/oxide interface. Other proposed solutions for mitigating the nonlinearities due to the high resistivity silicon wafer handle region interfaced with the BOX dielectric region include harmonic suppression process techniques that include a series of process steps and heating treatments to minimize nonlinearities attributed to the high resistivity handle region interfaced with the BOX dielectric region. However, all the aforementioned proposed solutions add significant complexity and cost to CMOS SOI technology. What is needed are CMOS SOI-based semiconductor devices and methods for manufacturing CMOS SOI devices that do not produce the nonlinearities attributed to the high resistivity silicon wafer handle region interfaced with the BOX dielectric region.